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author | Tristan Gingold <tgingold@free.fr> | 2019-09-04 06:52:35 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-04 06:52:35 +0200 |
commit | 4cb565baea6e93f804bef253200f0872428a3daa (patch) | |
tree | 6ed5ee76fe6c1c9e52d94a03666e1d121ccfd094 /testsuite/synth/dispin01/tb_rec03.vhdl | |
parent | 95433bc986b16badf5a48ab00df861d0424ca983 (diff) | |
download | ghdl-4cb565baea6e93f804bef253200f0872428a3daa.tar.gz ghdl-4cb565baea6e93f804bef253200f0872428a3daa.tar.bz2 ghdl-4cb565baea6e93f804bef253200f0872428a3daa.zip |
testsuite/synth: rename disp01 to dispin01
Diffstat (limited to 'testsuite/synth/dispin01/tb_rec03.vhdl')
-rw-r--r-- | testsuite/synth/dispin01/tb_rec03.vhdl | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/testsuite/synth/dispin01/tb_rec03.vhdl b/testsuite/synth/dispin01/tb_rec03.vhdl new file mode 100644 index 000000000..7495ac183 --- /dev/null +++ b/testsuite/synth/dispin01/tb_rec03.vhdl @@ -0,0 +1,39 @@ +entity tb_rec03 is +end tb_rec03; + +library ieee; +use ieee.std_logic_1164.all; +use work.rec03_pkg.all; + +architecture behav of tb_rec03 is + signal inp : myrec; + signal r : std_logic; +begin + dut: entity work.rec03 + port map (inp => inp, o => r); + + process + begin + inp.a <= s0; + inp.b <= '1'; + wait for 1 ns; + assert r = '1' severity failure; + + inp.a <= s2; + inp.b <= '1'; + wait for 1 ns; + assert r = '1' severity failure; + + inp.a <= s2; + inp.b <= '0'; + wait for 1 ns; + assert r = '0' severity failure; + + inp.a <= s3; + inp.b <= '0'; + wait for 1 ns; + assert r = '1' severity failure; + + wait; + end process; +end behav; |