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authorTristan Gingold <tgingold@free.fr>2019-09-13 07:28:55 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-13 07:28:55 +0200
commit32fee63a7b9d7fd5b86c1efc7280441e7d0dbf1f (patch)
treea776901d4525e7120732e0bf688036de5381837c /testsuite/synth/func01/tb_func02.vhdl
parent2e61401a3d12ede4bb72bc6749d7f6ae905d6376 (diff)
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testsuite/synth: add more tests in func01.
Diffstat (limited to 'testsuite/synth/func01/tb_func02.vhdl')
-rw-r--r--testsuite/synth/func01/tb_func02.vhdl29
1 files changed, 29 insertions, 0 deletions
diff --git a/testsuite/synth/func01/tb_func02.vhdl b/testsuite/synth/func01/tb_func02.vhdl
new file mode 100644
index 000000000..c00db3a3a
--- /dev/null
+++ b/testsuite/synth/func01/tb_func02.vhdl
@@ -0,0 +1,29 @@
+entity tb_func02 is
+end tb_func02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_func02 is
+ signal a, b : std_logic_vector(7 downto 0);
+begin
+ dut: entity work.func02
+ port map (a, b);
+
+ process
+ begin
+ a <= x"5d";
+ wait for 1 ns;
+ assert b = x"01" severity failure;
+
+ a <= x"ff";
+ wait for 1 ns;
+ assert b = x"01" severity failure;
+
+ a <= x"fe";
+ wait for 1 ns;
+ assert b = x"00" severity failure;
+
+ wait;
+ end process;
+end behav;