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author | Tristan Gingold <tgingold@free.fr> | 2019-07-25 05:35:03 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-25 05:35:03 +0200 |
commit | e5aa8272090bba9224b6e544113ff8b2bce0dd33 (patch) | |
tree | 3d68a7557b0cc12eb9db7147c54ab07d5c41d21c /testsuite/synth/insert01/insert02.vhdl | |
parent | fe4cf1f80f6c805e629e6909d259d17a915b05e3 (diff) | |
download | ghdl-e5aa8272090bba9224b6e544113ff8b2bce0dd33.tar.gz ghdl-e5aa8272090bba9224b6e544113ff8b2bce0dd33.tar.bz2 ghdl-e5aa8272090bba9224b6e544113ff8b2bce0dd33.zip |
synth: add test for previous commit.
Diffstat (limited to 'testsuite/synth/insert01/insert02.vhdl')
-rw-r--r-- | testsuite/synth/insert01/insert02.vhdl | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/testsuite/synth/insert01/insert02.vhdl b/testsuite/synth/insert01/insert02.vhdl new file mode 100644 index 000000000..5f7b7e6c3 --- /dev/null +++ b/testsuite/synth/insert01/insert02.vhdl @@ -0,0 +1,23 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity insert02 is + port (a : std_logic_vector (3 downto 0); + b : std_logic_vector (1 downto 0); + o0, o1, o2 : out std_logic_vector (3 downto 0)); +end insert02; + +architecture behav of insert02 is +begin + process(a, b) + begin + o0 <= a; + o0 (1 downto 0) <= b; + + o1 <= a; + o1 (2 downto 1) <= b; + + o2 <= a; + o2 (3 downto 2) <= b; + end process; +end behav; |