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authorTristan Gingold <tgingold@free.fr>2020-05-03 19:31:37 +0200
committerTristan Gingold <tgingold@free.fr>2020-05-04 19:04:10 +0200
commit6d6ee6778edcbca12bc322839c061fe788bb86ba (patch)
tree96abbee06dc1fa9148af5ca5be0da56fb7acb23e /testsuite/synth/int01/prio02.vhdl
parenta5f991845596105b0476b219822f7ad8c7c857c8 (diff)
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testsuite/synth: add a regression test for previous commits.
Diffstat (limited to 'testsuite/synth/int01/prio02.vhdl')
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diff --git a/testsuite/synth/int01/prio02.vhdl b/testsuite/synth/int01/prio02.vhdl
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+++ b/testsuite/synth/int01/prio02.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity prio02 is
+ port (dat : std_logic_vector(15 downto 0);
+ prio : out natural);
+end;
+
+architecture behav of prio02 is
+ function prioritize(b : std_logic_vector(15 downto 0)) return natural
+ is
+ variable level : integer range 0 to 15;
+ begin
+ level := 0;
+ for i in 15 downto 0 loop
+ level := i;
+ if b(i) = '1' then exit; end if;
+ end loop;
+ return level;
+ end;
+begin
+ prio <= prioritize (dat);
+end;
+