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authorTristan Gingold <tgingold@free.fr>2019-11-12 20:35:15 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-12 20:36:05 +0100
commit329df90440cc4bf53229afe16f84ec4caa50e8bf (patch)
treeda232b483424d212ffcf8f4539b120400164248b /testsuite/synth/issue1014/record_test.vhdl
parent987fa0d6f09a71073dce20657917f87178fb7cb1 (diff)
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testsuite/synth: add testcase for #1014
Diffstat (limited to 'testsuite/synth/issue1014/record_test.vhdl')
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diff --git a/testsuite/synth/issue1014/record_test.vhdl b/testsuite/synth/issue1014/record_test.vhdl
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+library ieee;
+ use ieee.std_logic_1164.all;
+
+entity record_test is
+ port (
+ o : out integer
+ );
+end record_test;
+
+architecture rtl of record_test is
+ type t_record is record
+ int : integer;
+ end record t_record;
+
+ function get_constants(choice : std_logic) return t_record is
+ variable v_const : t_record;
+ begin
+ if choice = '0' then
+ v_const := (int => 27.777 us / 83.333 ns);
+ elsif choice = '1' then
+ v_const := (int => 26.316 us / 83.333 ns);
+ end if;
+ return v_const;
+ end function get_constants;
+
+ constant rec_constant : t_record := get_constants('0');
+ signal int_test : integer range 0 to rec_constant.int := 0;
+ signal slv_test : std_logic_vector(rec_constant.int downto 0) := (others => '0');
+begin
+ o <= rec_constant.int;
+end rtl;