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author | Tristan Gingold <tgingold@free.fr> | 2019-11-29 19:09:13 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-11-29 19:09:13 +0100 |
commit | 75d82a9f92a1845ae933d2599cddf92f938446af (patch) | |
tree | 5a5f9c2c1b3b0a5cb54dee204562aa19d5603050 /testsuite/synth/issue1046/concat01.vhdl | |
parent | 09de5ec9c9e8c66b2690c53b4e89ce81c5d447e5 (diff) | |
download | ghdl-75d82a9f92a1845ae933d2599cddf92f938446af.tar.gz ghdl-75d82a9f92a1845ae933d2599cddf92f938446af.tar.bz2 ghdl-75d82a9f92a1845ae933d2599cddf92f938446af.zip |
testsuite: add case for #1046
Diffstat (limited to 'testsuite/synth/issue1046/concat01.vhdl')
-rw-r--r-- | testsuite/synth/issue1046/concat01.vhdl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/synth/issue1046/concat01.vhdl b/testsuite/synth/issue1046/concat01.vhdl new file mode 100644 index 000000000..12f817d8d --- /dev/null +++ b/testsuite/synth/issue1046/concat01.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity concat01 is + generic (a : std_logic_vector (7 downto 0) := x"ab"; + b : std_logic_vector (7 downto 0) := x"9e"); + port (res : out std_logic_vector (15 downto 0)); +end concat01; + +architecture behav of concat01 is + constant c : std_logic_vector := a & b; +begin + res <= c; +end behav; |