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authorTristan Gingold <tgingold@free.fr>2019-11-29 19:09:13 +0100
committerTristan Gingold <tgingold@free.fr>2019-11-29 19:09:13 +0100
commit75d82a9f92a1845ae933d2599cddf92f938446af (patch)
tree5a5f9c2c1b3b0a5cb54dee204562aa19d5603050 /testsuite/synth/issue1046/concat01.vhdl
parent09de5ec9c9e8c66b2690c53b4e89ce81c5d447e5 (diff)
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testsuite: add case for #1046
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-rw-r--r--testsuite/synth/issue1046/concat01.vhdl14
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diff --git a/testsuite/synth/issue1046/concat01.vhdl b/testsuite/synth/issue1046/concat01.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity concat01 is
+ generic (a : std_logic_vector (7 downto 0) := x"ab";
+ b : std_logic_vector (7 downto 0) := x"9e");
+ port (res : out std_logic_vector (15 downto 0));
+end concat01;
+
+architecture behav of concat01 is
+ constant c : std_logic_vector := a & b;
+begin
+ res <= c;
+end behav;