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author | Tristan Gingold <tgingold@free.fr> | 2019-12-24 18:01:07 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-12-24 18:01:07 +0100 |
commit | 0c8d0c455f12bf59a1d0b2c1eefddd1a319efe00 (patch) | |
tree | 3b5635767bb6139542a954e1c17728908141c219 /testsuite/synth/issue1054/simple01.vhdl | |
parent | e0a1519e89fbc896517ced756719679e223c5401 (diff) | |
download | ghdl-0c8d0c455f12bf59a1d0b2c1eefddd1a319efe00.tar.gz ghdl-0c8d0c455f12bf59a1d0b2c1eefddd1a319efe00.tar.bz2 ghdl-0c8d0c455f12bf59a1d0b2c1eefddd1a319efe00.zip |
testsuite/synth: add testcase for #1054
Diffstat (limited to 'testsuite/synth/issue1054/simple01.vhdl')
-rw-r--r-- | testsuite/synth/issue1054/simple01.vhdl | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/testsuite/synth/issue1054/simple01.vhdl b/testsuite/synth/issue1054/simple01.vhdl new file mode 100644 index 000000000..28495def5 --- /dev/null +++ b/testsuite/synth/issue1054/simple01.vhdl @@ -0,0 +1,20 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity simple01 is + port (a, b, c : in std_logic; + z : out std_logic); +end simple01; + +architecture behav of simple01 is +begin + process(A, B, C) + variable temp : std_logic; + begin + if is_x (a) then + z <= b; + else + z <= b or c; + end if; + end process; +end behav; |