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authorTristan Gingold <tgingold@free.fr>2020-05-31 10:14:56 +0200
committerTristan Gingold <tgingold@free.fr>2020-05-31 10:14:56 +0200
commit8f6a304b35ace79ea50a21151e05a1ab2dce25e0 (patch)
tree20da49441a98fdda608f54742b5ee8be08244d87 /testsuite/synth/issue1069/ram4.vhdl
parentdb7ad329681b321491aea1e458f55adc8068c90b (diff)
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testsuite/synth: add more tests for #1069
Diffstat (limited to 'testsuite/synth/issue1069/ram4.vhdl')
-rw-r--r--testsuite/synth/issue1069/ram4.vhdl8
1 files changed, 4 insertions, 4 deletions
diff --git a/testsuite/synth/issue1069/ram4.vhdl b/testsuite/synth/issue1069/ram4.vhdl
index 3321e59c1..41792e8b3 100644
--- a/testsuite/synth/issue1069/ram4.vhdl
+++ b/testsuite/synth/issue1069/ram4.vhdl
@@ -2,9 +2,9 @@ library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
-entity tdp_ram is
+entity ram4 is
generic (
- ADDRWIDTH : positive := 7;
+ ADDRWIDTH : positive := 12;
WIDTH : positive := 8
);
port (
@@ -22,9 +22,9 @@ entity tdp_ram is
data_read_b : out std_logic_vector(WIDTH - 1 downto 0);
data_write_b : in std_logic_vector(WIDTH - 1 downto 0)
);
-end tdp_ram;
+end ram4;
-architecture behavioral of tdp_ram is
+architecture behavioral of ram4 is
begin
process(clk_a, clk_b)
type ram_t is array(0 to 2**ADDRWIDTH - 1) of std_logic_vector(WIDTH - 1 downto 0);