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author | Tristan Gingold <tgingold@free.fr> | 2020-01-11 07:07:32 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-01-11 07:07:32 +0100 |
commit | 4d148edb4087a0a14172d27d037e59d8874c66b9 (patch) | |
tree | bc262d0ca3c41c7b70031febd8f733c7c7fba529 /testsuite/synth/issue1076/ent.vhdl | |
parent | 03d7679ae8d834bba4e175318ada25db33ef2944 (diff) | |
download | ghdl-4d148edb4087a0a14172d27d037e59d8874c66b9.tar.gz ghdl-4d148edb4087a0a14172d27d037e59d8874c66b9.tar.bz2 ghdl-4d148edb4087a0a14172d27d037e59d8874c66b9.zip |
testsuite/synth: add a test for #1076
Diffstat (limited to 'testsuite/synth/issue1076/ent.vhdl')
-rw-r--r-- | testsuite/synth/issue1076/ent.vhdl | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/synth/issue1076/ent.vhdl b/testsuite/synth/issue1076/ent.vhdl new file mode 100644 index 000000000..88dc7ccab --- /dev/null +++ b/testsuite/synth/issue1076/ent.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent is + port ( + o : out std_logic + ); +end; + +architecture a of ent is +begin + gen: if false generate + o <= '1'; + else generate + o <= '0'; + end generate; +end; + |