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author | Tristan Gingold <tgingold@free.fr> | 2020-02-17 18:37:57 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-02-17 18:37:57 +0100 |
commit | 9ee1a4a1e7531ec40cef8501edf312873223209b (patch) | |
tree | b0fae9e1bd354b5d0360e3efb18a9aaa4ec65cbc /testsuite/synth/issue1076/ent3.vhdl | |
parent | 55f28c3f2473cf41f83ae63ef52223e8cbfe9016 (diff) | |
download | ghdl-9ee1a4a1e7531ec40cef8501edf312873223209b.tar.gz ghdl-9ee1a4a1e7531ec40cef8501edf312873223209b.tar.bz2 ghdl-9ee1a4a1e7531ec40cef8501edf312873223209b.zip |
testsuite/synth: add a test for #1076
Diffstat (limited to 'testsuite/synth/issue1076/ent3.vhdl')
-rw-r--r-- | testsuite/synth/issue1076/ent3.vhdl | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/testsuite/synth/issue1076/ent3.vhdl b/testsuite/synth/issue1076/ent3.vhdl new file mode 100644 index 000000000..fd81a9ca9 --- /dev/null +++ b/testsuite/synth/issue1076/ent3.vhdl @@ -0,0 +1,65 @@ +library ieee; +use ieee.std_logic_1164.all; + +library work; + use work.ext_comp.all; + +entity ent is + -- This case works. + -- generic ( CONFIG_C1: boolean := false ); + port ( + i : in std_logic; + o : out std_logic; + q : out std_logic + ); + constant CONFIG_C1 : boolean := false; +end; + +architecture a of ent is + +begin + gen: if false generate + o <= '1'; + else generate + o <= '0'; + end generate; + +maybe_c1: + if CONFIG_C1 generate + c1_inst: c1 port map (i => i, o=> q); + end generate; + +maybe_c2: + if not CONFIG_C1 generate + c2_inst: c2 port map (i => i, o=> q); + end generate; + + +end; + +-- Added entities to satisfy simulation: + +library ieee; +use ieee.std_logic_1164.all; + +entity c1 is + port (i: in std_logic; o : out std_logic); +end entity; + +architecture a of c1 is +begin + o <= i; +end a; + +library ieee; +use ieee.std_logic_1164.all; + +entity c2 is + port (i: in std_logic; o : out std_logic); +end entity; + +architecture a of c2 is +begin + o <= i; +end a; + |