testsuite/synth: add test for previous commit

5 files changed, 193 insertions, 0 deletions

diff --git a/testsuite/synth/issue1079/tb_test2.vhdl b/testsuite/synth/issue1079/tb_test2.vhdl
new file mode 100644
index 000000000..27f6037b0
--- /dev/null
+++ b/testsuite/synth/issue1079/tb_test2.vhdl
@@ -0,0 +1,58 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_test2 is
+end;
+
+architecture behav of tb_test2 is
+  signal clk     : std_logic;
+  signal rd_en   : std_logic;
+  signal rd_addr : std_logic_vector(7 downto 0);
+  signal rd_data : std_logic_vector(63 downto 0);
+  signal wr_en   : std_logic;
+  signal wr_sel  : std_logic_vector(7 downto 0);
+  signal wr_addr : std_logic_vector(7 downto 0);
+  signal wr_data : std_logic_vector(63 downto 0);
+begin
+  inst_test2: entity work.test2
+    port map (
+      clk     => clk,
+      rd_en   => rd_en,
+      rd_addr => rd_addr,
+      rd_data => rd_data,
+      wr_en   => wr_en,
+      wr_sel  => wr_sel,
+      wr_addr => wr_addr,
+      wr_data => wr_data);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 5 ns;
+      clk <= '1';
+      wait for 5 ns;
+    end pulse;
+  begin
+    rd_en <= '0';
+    wr_en <= '0';
+    wr_sel <= x"ff";
+    pulse;
+
+    wr_en <= '1';
+    wr_addr <= x"01";
+    wr_data <= x"01_12_34_56_78_9a_bc_de";
+    pulse;
+
+    wr_en <= '1';
+    wr_addr <= x"02";
+    wr_data <= x"02_12_34_56_78_9a_bc_de";
+
+    rd_en <= '1';
+    rd_addr <= x"01";
+    pulse;
+
+    assert rd_data = x"01_12_34_56_78_9a_bc_de";
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1079/tb_test2n.vhdl b/testsuite/synth/issue1079/tb_test2n.vhdl
new file mode 100644
index 000000000..90f975f1c
--- /dev/null
+++ b/testsuite/synth/issue1079/tb_test2n.vhdl
@@ -0,0 +1,53 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_test2n is
+end;
+
+architecture behav of tb_test2n is
+  signal clk     : std_logic;
+  signal rd_addr : std_logic_vector(7 downto 0);
+  signal rd_data : std_logic_vector(63 downto 0);
+  signal en   : std_logic;
+  signal wr_sel  : std_logic_vector(7 downto 0);
+  signal wr_addr : std_logic_vector(7 downto 0);
+  signal wr_data : std_logic_vector(63 downto 0);
+begin
+  inst_test2n: entity work.test2n
+    port map (
+      clk     => clk,
+      en      => en,
+      rd_addr => rd_addr,
+      rd_data => rd_data,
+      wr_sel  => wr_sel,
+      wr_addr => wr_addr,
+      wr_data => wr_data);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 5 ns;
+      clk <= '1';
+      wait for 5 ns;
+    end pulse;
+  begin
+    en <= '0';
+    wr_sel <= x"ff";
+    pulse;
+
+    en <= '1';
+    wr_addr <= x"01";
+    wr_data <= x"01_12_34_56_78_9a_bc_de";
+    pulse;
+
+    wr_addr <= x"02";
+    wr_data <= x"02_12_34_56_78_9a_bc_de";
+
+    rd_addr <= x"01";
+    pulse;
+
+    assert rd_data = x"01_12_34_56_78_9a_bc_de";
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1079/test2.vhdl b/testsuite/synth/issue1079/test2.vhdl
new file mode 100644
index 000000000..a3234e0d9
--- /dev/null
+++ b/testsuite/synth/issue1079/test2.vhdl
@@ -0,0 +1,41 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test2 is
+    port(
+	clk     : in  std_logic;
+
+	rd_en   : in  std_logic;
+	rd_addr : in  std_logic_vector(7 downto 0);
+	rd_data : out std_logic_vector(63 downto 0);
+
+	wr_en   : in  std_logic;
+	wr_sel  : in  std_logic_vector(7 downto 0);
+	wr_addr : in  std_logic_vector(7 downto 0);
+	wr_data : in  std_logic_vector(63 downto 0)
+	);
+end test2;
+
+architecture rtl of test2 is
+    constant SIZE : integer := 2**8;
+    type ram_type is array (0 to SIZE - 1) of std_logic_vector(63 downto 0);
+    signal ram : ram_type;
+    signal rd_data0 : std_logic_vector(63 downto 0);
+begin
+    process(clk)
+	variable widx : integer range 0 to SIZE - 1;
+    begin
+	if rising_edge(clk) then
+	    if wr_en = '1' then
+		widx := to_integer(unsigned(wr_addr));
+                ram(widx) <= wr_data;
+	    end if;
+	    if rd_en = '1' then
+		rd_data0 <= ram(to_integer(unsigned(rd_addr)));
+	    end if;
+	end if;
+    end process;
+
+    rd_data <= rd_data0;
+end;
diff --git a/testsuite/synth/issue1079/test2n.vhdl b/testsuite/synth/issue1079/test2n.vhdl
new file mode 100644
index 000000000..f1890825d
--- /dev/null
+++ b/testsuite/synth/issue1079/test2n.vhdl
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test2n is
+    port(
+	clk     : in  std_logic;
+	en   : in  std_logic;
+
+	rd_addr : in  std_logic_vector(7 downto 0);
+	rd_data : out std_logic_vector(63 downto 0);
+
+	wr_sel  : in  std_logic_vector(7 downto 0);
+	wr_addr : in  std_logic_vector(7 downto 0);
+	wr_data : in  std_logic_vector(63 downto 0)
+	);
+end test2n;
+
+architecture rtl of test2n is
+    constant SIZE : integer := 2**8;
+    type ram_type is array (0 to SIZE - 1) of std_logic_vector(63 downto 0);
+    signal ram : ram_type;
+    signal rd_data0 : std_logic_vector(63 downto 0);
+begin
+    process(clk)
+	variable widx : integer range 0 to SIZE - 1;
+    begin
+	if rising_edge(clk) then
+	    if en /= '0' then
+		widx := to_integer(unsigned(wr_addr));
+                ram(widx) <= wr_data;
+		rd_data0 <= ram(to_integer(unsigned(rd_addr)));
+	    end if;
+	end if;
+    end process;
+
+    rd_data <= rd_data0;
+end;
diff --git a/testsuite/synth/issue1079/testsuite.sh b/testsuite/synth/issue1079/testsuite.sh
index 875f6aa57..4c17ce169 100755
--- a/testsuite/synth/issue1079/testsuite.sh
+++ b/testsuite/synth/issue1079/testsuite.sh
@@ -5,4 +5,7 @@
 synth --out=raw test.vhdl -e > syn_test.raw
 grep -q mem_rd_sync syn_test.raw
 
+synth_tb test2
+synth_tb test2n
+
 echo "Test successful"