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| author | Tristan Gingold <tgingold@free.fr> | 2021-11-28 18:15:29 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-11-28 18:15:29 +0100 |
| commit | 0416c788cd9aecd1a2bc8e7a517606d181d99921 (patch) | |
| tree | 4c3a8886cca8fb996f42118696e9369656018084 /testsuite/synth/issue1090/tb_simple_ram.vhdl | |
| parent | c7d32abe6f8108c0e7af6eea5d546be2bd83b704 (diff) | |
| download | ghdl-0416c788cd9aecd1a2bc8e7a517606d181d99921.tar.gz ghdl-0416c788cd9aecd1a2bc8e7a517606d181d99921.tar.bz2 ghdl-0416c788cd9aecd1a2bc8e7a517606d181d99921.zip | |
testsuite/synth: avoid use of verilog identifiers
Diffstat (limited to 'testsuite/synth/issue1090/tb_simple_ram.vhdl')
| -rw-r--r-- | testsuite/synth/issue1090/tb_simple_ram.vhdl | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/testsuite/synth/issue1090/tb_simple_ram.vhdl b/testsuite/synth/issue1090/tb_simple_ram.vhdl index 437c6543a..e5f515c21 100644 --- a/testsuite/synth/issue1090/tb_simple_ram.vhdl +++ b/testsuite/synth/issue1090/tb_simple_ram.vhdl @@ -15,8 +15,8 @@ architecture behav of tb_simple_ram is begin dut: entity work.simple_ram port map (clk => clk, - en => en, raddr => raddr, do => rdat, - we => we, waddr => waddr, di => wdat); + en => en, raddr => raddr, dout => rdat, + we => we, waddr => waddr, din => wdat); process procedure pulse is |