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authorTristan Gingold <tgingold@free.fr>2020-02-01 11:22:08 +0100
committerTristan Gingold <tgingold@free.fr>2020-02-01 11:22:08 +0100
commit1fe0dce8f25255bcf9a3a3cfe317f763f1e410ce (patch)
tree4c8b724922c40afe9492c559d7ba93e2d68b6c81 /testsuite/synth/issue1122/repro2.vhdl
parent579d59ed60396da77f015da6e86fce80c53dbeda (diff)
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testsuite/synth: add tests for #1122
Diffstat (limited to 'testsuite/synth/issue1122/repro2.vhdl')
-rw-r--r--testsuite/synth/issue1122/repro2.vhdl22
1 files changed, 22 insertions, 0 deletions
diff --git a/testsuite/synth/issue1122/repro2.vhdl b/testsuite/synth/issue1122/repro2.vhdl
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+++ b/testsuite/synth/issue1122/repro2.vhdl
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+entity repro2 is
+ port (clk : bit;
+ rst : bit;
+ d : bit;
+ q : out bit);
+end repro2;
+
+architecture behav of repro2 is
+ constant c : bit := '1';
+ signal s : bit := c;
+begin
+ process (clk)
+ begin
+ if rst = '1' then
+ s <= c;
+ elsif clk = '1' and clk'event then
+ s <= d;
+ end if;
+ end process;
+
+ q <= s;
+end behav;