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author | Tristan Gingold <tgingold@free.fr> | 2020-03-18 07:33:44 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-18 07:33:44 +0100 |
commit | 2d50c68e91dcaafabb52d02afd43e001955b6b03 (patch) | |
tree | bab543756121eaf172b3725d821c9334c455d07b /testsuite/synth/issue1160/issue.vhdl | |
parent | 3939ce510a2eaa7f612078369a9032e12981efb1 (diff) | |
download | ghdl-2d50c68e91dcaafabb52d02afd43e001955b6b03.tar.gz ghdl-2d50c68e91dcaafabb52d02afd43e001955b6b03.tar.bz2 ghdl-2d50c68e91dcaafabb52d02afd43e001955b6b03.zip |
testsuite/synth: add a test for #1160
Diffstat (limited to 'testsuite/synth/issue1160/issue.vhdl')
-rw-r--r-- | testsuite/synth/issue1160/issue.vhdl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/synth/issue1160/issue.vhdl b/testsuite/synth/issue1160/issue.vhdl new file mode 100644 index 000000000..36f2890ba --- /dev/null +++ b/testsuite/synth/issue1160/issue.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity issue is + generic (N : natural := 3); + port (data : out signed(N-1 downto 0)); +end issue; + +architecture rtl of issue is + subtype my_type is signed(N-1 downto 0); +begin + data <= to_signed(1,my_type'length); +end architecture; |