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authorTristan Gingold <tgingold@free.fr>2020-03-19 08:56:05 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-19 08:56:05 +0100
commit7a6ab8c14858a09b87be025e267eff5192e99c08 (patch)
tree7b9f39526c599424445ea3f8bbd40fa656f7c4b7 /testsuite/synth/issue1161/issue3.vhdl
parent1f576163e1fb20887557f1a20b444a558a3c0239 (diff)
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testsuite/synth: add a test for #1161
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diff --git a/testsuite/synth/issue1161/issue3.vhdl b/testsuite/synth/issue1161/issue3.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity issue3 is
+ port (foo : out std_logic_vector(4-1 downto 0));
+end issue3;
+
+architecture rtl of issue3 is
+begin
+ foo <= ("01", "10");
+end architecture;