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authorTristan Gingold <tgingold@free.fr>2020-03-19 08:56:05 +0100
committerTristan Gingold <tgingold@free.fr>2020-03-19 08:56:05 +0100
commit7a6ab8c14858a09b87be025e267eff5192e99c08 (patch)
tree7b9f39526c599424445ea3f8bbd40fa656f7c4b7 /testsuite/synth/issue1161/tb_issue1.vhdl
parent1f576163e1fb20887557f1a20b444a558a3c0239 (diff)
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testsuite/synth: add a test for #1161
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-rw-r--r--testsuite/synth/issue1161/tb_issue1.vhdl19
1 files changed, 19 insertions, 0 deletions
diff --git a/testsuite/synth/issue1161/tb_issue1.vhdl b/testsuite/synth/issue1161/tb_issue1.vhdl
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+++ b/testsuite/synth/issue1161/tb_issue1.vhdl
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+entity tb_issue1 is
+end tb_issue1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_issue1 is
+ signal a : std_logic_vector (3 downto 0);
+begin
+ dut: entity work.issue1
+ port map (a);
+
+ process
+ begin
+ wait for 1 ns;
+ assert a = "0111" severity failure;
+ wait;
+ end process;
+end behav;