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authorTristan Gingold <tgingold@free.fr>2020-04-09 22:04:30 +0200
committerTristan Gingold <tgingold@free.fr>2020-04-09 22:04:30 +0200
commit7bb42dba484fcbec66a97f613fa07a0299320443 (patch)
treeb6d2833a218aab1d0e535b65a215cf961ffe8d72 /testsuite/synth/issue1181/bug.vhdl
parentd0af178e8f4a5387303727630a9a0690a1627ada (diff)
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testsuite/synth: add a case for #1181
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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+ port(
+ dummy : in std_ulogic
+ );
+end bug;
+
+architecture behav of bug is
+begin
+ process(all)
+ variable index : integer;
+ begin
+ index := 10;
+ if index > 3 then
+ -- index := index-1;
+ end if;
+ end process;
+
+end architecture;