synth: add testcase for concurrent selected signal assignment.

1 files changed, 25 insertions, 0 deletions

diff --git a/testsuite/synth/issue12/lut.vhdl b/testsuite/synth/issue12/lut.vhdl
new file mode 100644
index 000000000..5c04e8d9a
--- /dev/null
+++ b/testsuite/synth/issue12/lut.vhdl
@@ -0,0 +1,25 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity lut is port (
+    sel: in std_logic_vector (1 downto 0);
+    c: out std_logic);
+end lut;
+
+-- sel(1)  sel(0) |  c 
+--   0       0    |  1    
+--   0       1    |  0
+--   1       0    |  1
+--   1       1    |  0
+
+architecture synth of lut is
+begin
+
+with sel select c <=
+
+    '1' when "00",
+    '0' when "01",
+    '1' when "10",
+    '0' when others;
+
+end synth;