diff options
author | Tristan Gingold <tgingold@free.fr> | 2020-04-19 11:54:42 +0200 |
---|---|---|
committer | Tristan Gingold <tgingold@free.fr> | 2020-04-19 11:54:42 +0200 |
commit | 8fb42ce39ad5392557b281fa3d607bb7c6d79c5e (patch) | |
tree | e2752b7675d89a823a05fc2b652a6bfbc373bf7c /testsuite/synth/issue1239 | |
parent | 7a2c53cd09def758fa05f7db2d696fe73d05f543 (diff) | |
download | ghdl-8fb42ce39ad5392557b281fa3d607bb7c6d79c5e.tar.gz ghdl-8fb42ce39ad5392557b281fa3d607bb7c6d79c5e.tar.bz2 ghdl-8fb42ce39ad5392557b281fa3d607bb7c6d79c5e.zip |
testsuite/synth: add tests for #1239
Diffstat (limited to 'testsuite/synth/issue1239')
-rw-r--r-- | testsuite/synth/issue1239/repro2.vhdl | 18 | ||||
-rw-r--r-- | testsuite/synth/issue1239/repro3.vhdl | 18 | ||||
-rwxr-xr-x | testsuite/synth/issue1239/testsuite.sh | 3 |
3 files changed, 39 insertions, 0 deletions
diff --git a/testsuite/synth/issue1239/repro2.vhdl b/testsuite/synth/issue1239/repro2.vhdl new file mode 100644 index 000000000..53e77ea9a --- /dev/null +++ b/testsuite/synth/issue1239/repro2.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro2 is + generic ( + constant DIN_WIDTH : positive := 8; + constant F_SIZE : positive := 2 + ); +end repro2; + +architecture Behav of repro2 is + type SLIDING_WINDOW is array (0 to F_SIZE-1, 0 to F_SIZE-1) + of STD_LOGIC_VECTOR(DIN_WIDTH- 1 downto 0); + signal WINDOW: SLIDING_WINDOW; +begin + WINDOW <=(WINDOW 'range=> (WINDOW 'range=> (WINDOW 'range=>'0'))); +end Behav; + diff --git a/testsuite/synth/issue1239/repro3.vhdl b/testsuite/synth/issue1239/repro3.vhdl new file mode 100644 index 000000000..ab817ac1d --- /dev/null +++ b/testsuite/synth/issue1239/repro3.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity repro3 is + generic ( + constant DIN_WIDTH : positive := 8; + constant FIFO_DEPTH : positive := 12 + ); +end repro3; + +architecture Behav of repro3 is + type FIFO_Memory is array (0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR(DIN_WIDTH - 1 downto 0); + + signal FIFO_ROW_1 : FIFO_Memory; +begin + FIFO_ROW_1<= (FIFO_ROW_1 'range=> (FIFO_ROW_1 'range=>'0')); +end Behav; + diff --git a/testsuite/synth/issue1239/testsuite.sh b/testsuite/synth/issue1239/testsuite.sh index 6168864cb..40b97d0fc 100755 --- a/testsuite/synth/issue1239/testsuite.sh +++ b/testsuite/synth/issue1239/testsuite.sh @@ -5,4 +5,7 @@ GHDL_STD_FLAGS=-fsynopsys synth repro.vhdl -e > syn_repro.vhdl +synth_failure repro2.vhdl -e +synth_failure repro3.vhdl -e + echo "Test successful" |