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authorTristan Gingold <tgingold@free.fr>2020-05-06 08:22:10 +0200
committerTristan Gingold <tgingold@free.fr>2020-05-06 18:38:26 +0200
commitfa6147b879add9ad4db0f2bc8d4c47f7fd92f41c (patch)
treea9ca346ab1951833df6e8e09615e54346f0305f2 /testsuite/synth/issue1273/assert4.vhdl
parent3b70e630543da3d42fc0cda37389312d8910e0ab (diff)
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testsuite/synth: add more tests for #1273
Diffstat (limited to 'testsuite/synth/issue1273/assert4.vhdl')
-rw-r--r--testsuite/synth/issue1273/assert4.vhdl21
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/issue1273/assert4.vhdl b/testsuite/synth/issue1273/assert4.vhdl
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+++ b/testsuite/synth/issue1273/assert4.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity assert4 is
+ port (v : std_logic_Vector (7 downto 0);
+ en : std_logic;
+ clk : std_logic;
+ res : out std_logic);
+end;
+
+architecture behav of assert4 is
+begin
+ process (clk)
+ begin
+ if rising_edge(clk) and en = '1' then
+ assert v /= x"00";
+ res <= v(0) xor v(1);
+ end if;
+ end process;
+end behav;
+