testsuite/synth: add more tests for #1273

1 files changed, 26 insertions, 0 deletions

diff --git a/testsuite/synth/issue1273/assert7.vhdl b/testsuite/synth/issue1273/assert7.vhdl
new file mode 100644
index 000000000..d99642854
--- /dev/null
+++ b/testsuite/synth/issue1273/assert7.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity assert7 is
+  port (v : std_logic_Vector (7 downto 0);
+        en : std_logic;
+        clk : std_logic;
+        rst : std_logic;
+        res : out std_logic);
+end;
+
+architecture behav of assert7 is
+begin
+  process (clk, rst)
+  begin
+    if rst = '1' then
+      res <= '0';
+    elsif rising_edge(clk) and en = '1' then
+      assert v /= x"05";
+      assert v /= x"06";
+      assert v /= x"08";
+      res <= v(0) xor v(1);
+    end if;
+  end process;
+end behav;
+