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authorTristan Gingold <tgingold@free.fr>2020-05-04 06:27:49 +0200
committerTristan Gingold <tgingold@free.fr>2020-05-04 19:04:12 +0200
commit7dd90643ffceaaa61f71ecd19e51e898c31f6db7 (patch)
tree8f5a4eb123817124e5d3ccdf646f71943abfb954 /testsuite/synth/issue1280/issue.vhdl
parent6844b2e0b2bd14f9d359e13b08e1d916538b6289 (diff)
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testsuite/synth: add a test for #1280
Diffstat (limited to 'testsuite/synth/issue1280/issue.vhdl')
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diff --git a/testsuite/synth/issue1280/issue.vhdl b/testsuite/synth/issue1280/issue.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity issue is
+ generic (N : natural := 32);
+ port (foo : in std_logic_vector (N-1 downto 0);
+ bar_1 : out std_logic;
+ bar_2 : out std_logic);
+end issue;
+
+architecture beh of issue is
+ subtype slice1_t is natural range 9 downto 0;
+ subtype slice2_t is natural range slice1_t'high downto foo'low;
+begin
+ bar_1 <= or foo (slice1_t); -- works
+ bar_2 <= or foo (slice2_t); -- error and crashes
+end architecture beh;
+