testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.

3 files changed, 0 insertions, 75 deletions

diff --git a/testsuite/synth/issue12/lut.vhdl b/testsuite/synth/issue12/lut.vhdl
deleted file mode 100644
index 5c04e8d9a..000000000
--- a/testsuite/synth/issue12/lut.vhdl
+++ /dev/null
@@ -1,25 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity lut is port (
-    sel: in std_logic_vector (1 downto 0);
-    c: out std_logic);
-end lut;
-
--- sel(1)  sel(0) |  c 
---   0       0    |  1    
---   0       1    |  0
---   1       0    |  1
---   1       1    |  0
-
-architecture synth of lut is
-begin
-
-with sel select c <=
-
-    '1' when "00",
-    '0' when "01",
-    '1' when "10",
-    '0' when others;
-
-end synth;
diff --git a/testsuite/synth/issue12/tb_lut.vhdl b/testsuite/synth/issue12/tb_lut.vhdl
deleted file mode 100644
index f8f5cf3a6..000000000
--- a/testsuite/synth/issue12/tb_lut.vhdl
+++ /dev/null
@@ -1,34 +0,0 @@
-entity tb_lut is
-end tb_lut;
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-architecture behav of tb_lut is
-  signal c : std_logic;
-  signal s : std_logic_vector(1 downto 0);
-begin
-  dut: entity work.lut
-    port map (s, c);
-
-  process
-  begin
-    s <= "00";
-    wait for 1 ns;
-    assert c = '1' severity failure;
-
-    s <= "01";
-    wait for 1 ns;
-    assert c = '0' severity failure;
-
-    s <= "10";
-    wait for 1 ns;
-    assert c = '1' severity failure;
-
-    s <= "11";
-    wait for 1 ns;
-    assert c = '0' severity failure;
-
-    wait;
-  end process;
-end behav;
diff --git a/testsuite/synth/issue12/testsuite.sh b/testsuite/synth/issue12/testsuite.sh
deleted file mode 100755
index a65695152..000000000
--- a/testsuite/synth/issue12/testsuite.sh
+++ /dev/null
@@ -1,16 +0,0 @@
-#! /bin/sh
-
-. ../../testenv.sh
-
-for t in lut; do
-    analyze $t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
-
-    synth $t.vhdl -e $t > syn_$t.vhdl
-    analyze syn_$t.vhdl tb_$t.vhdl
-    elab_simulate tb_$t
-    clean
-done
-
-echo "Test successful"