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author | Tristan Gingold <tgingold@free.fr> | 2021-03-13 07:56:16 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-03-13 08:01:47 +0100 |
commit | 1f74b9c76a10dc727531996a134a933a242c022e (patch) | |
tree | 029c3e6a2b775e01eb73c82ea3f4875036fa46e3 /testsuite/synth/issue1681/test_fail.vhdl | |
parent | 02cb9db284e3d5caed826bfb104c5f948beec4b3 (diff) | |
download | ghdl-1f74b9c76a10dc727531996a134a933a242c022e.tar.gz ghdl-1f74b9c76a10dc727531996a134a933a242c022e.tar.bz2 ghdl-1f74b9c76a10dc727531996a134a933a242c022e.zip |
testsuite/synth: add a test for #1681
Diffstat (limited to 'testsuite/synth/issue1681/test_fail.vhdl')
-rw-r--r-- | testsuite/synth/issue1681/test_fail.vhdl | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/testsuite/synth/issue1681/test_fail.vhdl b/testsuite/synth/issue1681/test_fail.vhdl new file mode 100644 index 000000000..fc3301021 --- /dev/null +++ b/testsuite/synth/issue1681/test_fail.vhdl @@ -0,0 +1,37 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test_fail is + generic( + clock_count_c : natural range 1 to 2 := 2 + ); + port( + reset_n_i : in std_ulogic; + clock_i : in std_ulogic_vector(0 to clock_count_c-1) + ); + +end test_fail; + +architecture beh of test_fail is + + type regs_t is + record + foo: std_ulogic; + end record; + + signal r, rin: regs_t; + +begin + + regs: process (clock_i, reset_n_i) + begin + if clock_i(clock_count_c-1)'event and clock_i(clock_count_c-1) = '1' then + if reset_n_i = '0' then + r.foo <= '0'; + else + r <= rin; + end if; + end if; + end process; + +end architecture; |