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author | Tristan Gingold <tgingold@free.fr> | 2021-06-16 07:48:22 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-06-16 07:48:22 +0200 |
commit | 4c0f9967e541b914a207bd4419d62d00d3e1745c (patch) | |
tree | 8d5edcededa4d1aa4d167cffcbaceca6aae3e596 /testsuite/synth/issue1781/tb_simple2.vhdl | |
parent | 9a913ec7ac5bc2193ec3df90bf7f43808f5c80c6 (diff) | |
download | ghdl-4c0f9967e541b914a207bd4419d62d00d3e1745c.tar.gz ghdl-4c0f9967e541b914a207bd4419d62d00d3e1745c.tar.bz2 ghdl-4c0f9967e541b914a207bd4419d62d00d3e1745c.zip |
testsuite/synth: add test for #1781
Diffstat (limited to 'testsuite/synth/issue1781/tb_simple2.vhdl')
-rw-r--r-- | testsuite/synth/issue1781/tb_simple2.vhdl | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/testsuite/synth/issue1781/tb_simple2.vhdl b/testsuite/synth/issue1781/tb_simple2.vhdl new file mode 100644 index 000000000..5378ade4b --- /dev/null +++ b/testsuite/synth/issue1781/tb_simple2.vhdl @@ -0,0 +1,54 @@ +entity tb_simple2 is +end tb_simple2; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_simple2 is + signal addr : std_logic_vector(7 downto 0); + signal rdat : std_logic_vector(15 downto 0); + signal wdat : std_logic_vector(15 downto 0); + signal wren : std_logic; + signal rden : std_logic; + signal clk : std_logic; +begin + dut: entity work.simple2 + port map (clk_i => clk, rden_i => rden, wren_i => wren, + addr_i => addr, data_i => wdat, data_o => rdat); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + addr <= x"00"; + wdat <= x"0001"; + wren <= '1'; + rden <= '0'; + pulse; + + addr <= x"01"; + wdat <= x"0002"; + pulse; + + -- Simple read. + addr <= x"00"; + wren <= '0'; + rden <= '1'; + pulse; + assert rdat = x"0001" severity failure; + + -- Check write through. + addr <= x"03"; + wren <= '1'; + wdat <= x"3333"; + pulse; + assert rdat = x"3333" severity failure; + + wait; + end process; +end behav; |