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author | Tristan Gingold <tgingold@free.fr> | 2022-03-12 18:52:46 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-03-12 18:52:46 +0100 |
commit | aff48727a4d0ad4058b7d43a86ebd6ed24b9cc6d (patch) | |
tree | 96160d9e79f6ac2fb30efe411dfda4c81ffc8f9b /testsuite/synth/issue2002 | |
parent | b6f0ff834c3b221ab5b2380c871d76c83808493b (diff) | |
download | ghdl-aff48727a4d0ad4058b7d43a86ebd6ed24b9cc6d.tar.gz ghdl-aff48727a4d0ad4058b7d43a86ebd6ed24b9cc6d.tar.bz2 ghdl-aff48727a4d0ad4058b7d43a86ebd6ed24b9cc6d.zip |
testsuite/synth: add test for #2002
Diffstat (limited to 'testsuite/synth/issue2002')
-rw-r--r-- | testsuite/synth/issue2002/bug.vhdl | 14 | ||||
-rw-r--r-- | testsuite/synth/issue2002/synth_bug.ref | 6 | ||||
-rwxr-xr-x | testsuite/synth/issue2002/testsuite.sh | 8 |
3 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/synth/issue2002/bug.vhdl b/testsuite/synth/issue2002/bug.vhdl new file mode 100644 index 000000000..176dcea0d --- /dev/null +++ b/testsuite/synth/issue2002/bug.vhdl @@ -0,0 +1,14 @@ +library IEEE; +use IEEE.std_logic_1164.all; + +entity bug is + port ( + o : out std_ulogic_vector(33 downto 0) + ); +end bug; + +architecture struct of bug is + constant c : std_ulogic_vector(33 downto 0) := "0000000000000000000000000001111100"; +begin + o <= c; +end architecture; diff --git a/testsuite/synth/issue2002/synth_bug.ref b/testsuite/synth/issue2002/synth_bug.ref new file mode 100644 index 000000000..3f74c866d --- /dev/null +++ b/testsuite/synth/issue2002/synth_bug.ref @@ -0,0 +1,6 @@ +module bug + (output [33:0] o); + localparam [33:0] n1_o = 34'b0000000000000000000000000001111100; + assign o = n1_o; +endmodule + diff --git a/testsuite/synth/issue2002/testsuite.sh b/testsuite/synth/issue2002/testsuite.sh new file mode 100755 index 000000000..507fb72a3 --- /dev/null +++ b/testsuite/synth/issue2002/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +synth --out=verilog bug.vhdl -e > synth_bug.v +diff_nocr synth_bug.ref synth_bug.v + +echo "Test successful" |