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authorTristan Gingold <tgingold@free.fr>2022-06-04 16:37:23 +0200
committerTristan Gingold <tgingold@free.fr>2022-06-04 18:55:57 +0200
commit89afd0cc5a3b36f185c62c9f183066133631910e (patch)
tree1828a8e2d3285a8ed7dfc4b677c7dd0f9692f1de /testsuite/synth/issue2072/tb_swaptest.vhdl
parent467f6d66017b73496cef8b5212385c3b407a722f (diff)
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testsuite/synth: add a test for #2072
Diffstat (limited to 'testsuite/synth/issue2072/tb_swaptest.vhdl')
-rw-r--r--testsuite/synth/issue2072/tb_swaptest.vhdl37
1 files changed, 37 insertions, 0 deletions
diff --git a/testsuite/synth/issue2072/tb_swaptest.vhdl b/testsuite/synth/issue2072/tb_swaptest.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library std;
+use std.textio.all;
+
+entity tb_swaptest is
+end tb_swaptest;
+
+architecture behaviour of tb_swaptest
+is
+ constant clk_period : time := 10 ns;
+ signal clk : std_logic;
+ signal d : unsigned(7 downto 0) := X"c5";
+ signal q : unsigned(7 downto 0);
+begin
+
+ clk_process: process
+ begin
+ for i in 1 to 10 loop
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end loop;
+ wait;
+ end process;
+
+ st : entity work.swaptest
+ port map (
+ clk => clk,
+ d => d,
+ q => q
+ );
+
+end architecture;