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authorTristan Gingold <tgingold@free.fr>2022-07-05 06:32:49 +0200
committerTristan Gingold <tgingold@free.fr>2022-07-05 06:32:49 +0200
commit811dbc83d990ea31f78a4775ffa7434298d4b5ae (patch)
treec69fd02853eac7200a85f4c1124488b994f23348 /testsuite/synth/issue2124/b.vhdl
parent16294762f5e521c6a159b7946794119615dc0b39 (diff)
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testsuite/synth: add a test for #2124
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diff --git a/testsuite/synth/issue2124/b.vhdl b/testsuite/synth/issue2124/b.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity b is
+ port (
+ c : in std_logic;
+ d : in std_logic;
+ q : out std_logic
+ );
+end entity;
+
+architecture behaviour of b is
+begin
+
+ process (c)
+ begin
+ if rising_edge(c)
+ then
+ q <= d;
+ end if;
+ end process;
+
+end architecture;