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| author | Tristan Gingold <tgingold@free.fr> | 2022-08-14 21:55:05 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-08-14 21:55:05 +0200 |
| commit | 6d4fad2cb725799d2c7834cd0918e4036905f24e (patch) | |
| tree | 88aece00404d1d744ea3c2382639d8c5c2e201ca /testsuite/synth/issue2177/testsuite.sh | |
| parent | 153fbf23a362bc56275a009670e3de65e82b7987 (diff) | |
| download | ghdl-6d4fad2cb725799d2c7834cd0918e4036905f24e.tar.gz ghdl-6d4fad2cb725799d2c7834cd0918e4036905f24e.tar.bz2 ghdl-6d4fad2cb725799d2c7834cd0918e4036905f24e.zip | |
testsuite/synth: add a test for #2177
Diffstat (limited to 'testsuite/synth/issue2177/testsuite.sh')
| -rwxr-xr-x | testsuite/synth/issue2177/testsuite.sh | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/testsuite/synth/issue2177/testsuite.sh b/testsuite/synth/issue2177/testsuite.sh new file mode 100755 index 000000000..496e00805 --- /dev/null +++ b/testsuite/synth/issue2177/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + + +synth --out=verilog vlm5030_pack.vhd clock_functions_pack.vhd vlm5030_subcircuits.vhd vlm5030_gl.vhd -e > syn_vlm5030.v + +echo "Test successful" |