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author | Tristan Gingold <tgingold@free.fr> | 2022-12-22 08:09:08 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-12-22 08:09:08 +0100 |
commit | f05bbd02f16d3368e9c171a7f42a08f26219262d (patch) | |
tree | b997a17b4678eaa63e5d9adcaba62cfade8a6040 /testsuite/synth/issue2279/ent.vhdl | |
parent | 236f7eddef51acba2718eeda8431a1a68c7e231e (diff) | |
download | ghdl-f05bbd02f16d3368e9c171a7f42a08f26219262d.tar.gz ghdl-f05bbd02f16d3368e9c171a7f42a08f26219262d.tar.bz2 ghdl-f05bbd02f16d3368e9c171a7f42a08f26219262d.zip |
testsuite/synth: add a test for #2279
Diffstat (limited to 'testsuite/synth/issue2279/ent.vhdl')
-rw-r--r-- | testsuite/synth/issue2279/ent.vhdl | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/synth/issue2279/ent.vhdl b/testsuite/synth/issue2279/ent.vhdl new file mode 100644 index 000000000..6c33c60d3 --- /dev/null +++ b/testsuite/synth/issue2279/ent.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ent is + generic( + DATA_WIDTH : integer := 8 + ); +end; + +architecture arch of ent is + signal a : std_logic_vector(DATA_WIDTH-1 downto 0); + signal b : std_logic; + signal c : std_logic_vector(DATA_WIDTH+1-1 downto 0); +begin + (a, b) <= c; +end; + |