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author | Tristan Gingold <tgingold@free.fr> | 2023-01-30 20:34:47 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-01-30 20:34:47 +0100 |
commit | 50758607ddb6c5c96fc4d26e795cb37d83272768 (patch) | |
tree | 8e8c2ccc7f3df5e2e6bb92762379a070fe458b4c /testsuite/synth/issue2334/repro.vhdl | |
parent | 36f56bf6ec506072c19022de6a95055f3ededa99 (diff) | |
download | ghdl-50758607ddb6c5c96fc4d26e795cb37d83272768.tar.gz ghdl-50758607ddb6c5c96fc4d26e795cb37d83272768.tar.bz2 ghdl-50758607ddb6c5c96fc4d26e795cb37d83272768.zip |
testsuite/synth: add a test for #2334
Diffstat (limited to 'testsuite/synth/issue2334/repro.vhdl')
-rw-r--r-- | testsuite/synth/issue2334/repro.vhdl | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/issue2334/repro.vhdl b/testsuite/synth/issue2334/repro.vhdl new file mode 100644 index 000000000..7e8664fb7 --- /dev/null +++ b/testsuite/synth/issue2334/repro.vhdl @@ -0,0 +1,26 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ecp5pll is + generic (dynamic_en : natural := 0); + port ( + clk_i : in std_logic; + clk_o : out std_logic; + phasesel : in std_logic_vector(1 downto 0) := "00"); +end; + +architecture mix of ecp5pll is + type T_secondary is record + div : natural; + freq_string : string(0 to 9); + end record T_secondary; + + signal CLKOP_t : std_logic; + signal PHASESEL_HW : std_logic_vector(1 downto 0); +begin + G_dynamic: if dynamic_en /= 0 generate + PHASESEL_HW <= phasesel; + end generate; + + clk_o <= CLKOP_t; +end mix; |