testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.

1 files changed, 0 insertions, 42 deletions

diff --git a/testsuite/synth/issue34/repro_nat.vhdl b/testsuite/synth/issue34/repro_nat.vhdl
deleted file mode 100644
index 328c11781..000000000
--- a/testsuite/synth/issue34/repro_nat.vhdl
+++ /dev/null
@@ -1,42 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity sub_nat is
-  port (
-    clk : in std_logic;
-    a : in natural;
-    b : out natural
-  );
-end sub_nat;
-
-architecture rtl of sub_nat is
-begin
-  process(clk)
-  begin
-    if rising_edge(clk) then
-      b <= a;
-    end if;
-  end process;
-end rtl;
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity repro_nat is
-  port (
-    clk : in std_logic;
-    a : in natural;
-    b : out natural
-  );
-end repro_nat;
-
-architecture rtl of repro_nat is
-begin
-  i_sub_nat : entity work.sub_nat
-  port map (
-    clk => clk,
-    a => a,
-    b => b
-  );
-end rtl;