testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.

1 files changed, 0 insertions, 42 deletions

diff --git a/testsuite/synth/issue34/repro_rng1.vhdl b/testsuite/synth/issue34/repro_rng1.vhdl
deleted file mode 100644
index 9d5a70e04..000000000
--- a/testsuite/synth/issue34/repro_rng1.vhdl
+++ /dev/null
@@ -1,42 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity sub_rng1 is
-  port (
-    clk : in std_logic;
-    a : in natural range 0 to 7;
-    b : out natural range 0 to 7
-  );
-end sub_rng1;
-
-architecture rtl of sub_rng1 is
-begin
-  process(clk)
-  begin
-    if rising_edge(clk) then
-      b <= a;
-    end if;
-  end process;
-end rtl;
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-entity repro_rng1 is
-  port (
-    clk : in std_logic;
-    a : in natural range 0 to 7;
-    b : out natural range 0 to 7
-  );
-end repro_rng1;
-
-architecture rtl of repro_rng1 is
-begin
-  i_sub_rng1 : entity work.sub_rng1
-  port map (
-    clk => clk,
-    a => a,
-    b => b
-  );
-end rtl;