synth: add testcase for issue 34

1 files changed, 42 insertions, 0 deletions

diff --git a/testsuite/synth/issue34/repro_slv.vhdl b/testsuite/synth/issue34/repro_slv.vhdl
new file mode 100644
index 000000000..4b0e1b0e5
--- /dev/null
+++ b/testsuite/synth/issue34/repro_slv.vhdl
@@ -0,0 +1,42 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity sub_slv is
+  port (
+    clk : in std_logic;
+    a : in std_logic_vector(7 downto 0);
+    b : out std_logic_vector(7 downto 0)
+  );
+end sub_slv;
+
+architecture rtl of sub_slv is
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      b <= a;
+    end if;
+  end process;
+end rtl;
+
+
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity repro_slv is
+  port (
+    clk : in std_logic;
+    a : in std_logic_vector(7 downto 0);
+    b : out std_logic_vector(7 downto 0)
+  );
+end repro_slv;
+
+architecture rtl of repro_slv is
+begin
+  i_sub_slv : entity work.sub_slv
+  port map (
+    clk => clk,
+    a => a,
+    b => b
+  );
+end rtl;