synth: add testcase for issue 34

1 files changed, 20 insertions, 0 deletions

diff --git a/testsuite/synth/issue34/submodule.vhdl b/testsuite/synth/issue34/submodule.vhdl
new file mode 100644
index 000000000..bc282985a
--- /dev/null
+++ b/testsuite/synth/issue34/submodule.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity submodule is
+  port (
+    clk : in std_logic;
+    a : in std_logic_vector(7 downto 0);
+    b : out std_logic_vector(7 downto 0)
+  );
+end submodule;
+
+architecture rtl of submodule is
+begin
+  process(clk)
+  begin
+    if rising_edge(clk) then
+      b <= a;
+    end if;
+  end process;
+end rtl;