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authorTristan Gingold <tgingold@free.fr>2019-09-25 20:39:46 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-25 20:39:46 +0200
commit6e9336d11dfc4f53dba234e1f02a2b0172461e0c (patch)
tree12f93ed2cbbb62c0e8e2fb6b7124201fe0a216bd /testsuite/synth/issue34/tb_repro_nat.vhdl
parentdcc353b07b82a84f2aa598de3884c58f406e0652 (diff)
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testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.
Diffstat (limited to 'testsuite/synth/issue34/tb_repro_nat.vhdl')
-rw-r--r--testsuite/synth/issue34/tb_repro_nat.vhdl34
1 files changed, 0 insertions, 34 deletions
diff --git a/testsuite/synth/issue34/tb_repro_nat.vhdl b/testsuite/synth/issue34/tb_repro_nat.vhdl
deleted file mode 100644
index acfe72fea..000000000
--- a/testsuite/synth/issue34/tb_repro_nat.vhdl
+++ /dev/null
@@ -1,34 +0,0 @@
-entity tb_repro_nat is
-end tb_repro_nat;
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-architecture behav of tb_repro_nat is
- signal clk : std_logic;
- signal a : natural;
- signal b : natural;
-begin
- dut: entity work.repro_nat
- port map (
- clk => clk, a => a, b => b);
-
- process
- procedure pulse is
- begin
- clk <= '0';
- wait for 1 ns;
- clk <= '1';
- wait for 1 ns;
- end pulse;
- begin
- a <= 125;
- pulse;
- assert b = 125 severity failure;
-
- a <= 7689;
- pulse;
- assert b = 7689 severity failure;
- wait;
- end process;
-end behav;