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author | Tristan Gingold <tgingold@free.fr> | 2019-08-17 22:01:25 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-08-17 22:01:25 +0200 |
commit | e51f0ae6ee0a6c94b1a92b36dab7980d46b99668 (patch) | |
tree | db7e87da512315aaa47da48300700506bc5dd8c6 /testsuite/synth/issue34/tb_repro_rng1.vhdl | |
parent | f475ff49f316c373eab6579bb058508927534db9 (diff) | |
download | ghdl-e51f0ae6ee0a6c94b1a92b36dab7980d46b99668.tar.gz ghdl-e51f0ae6ee0a6c94b1a92b36dab7980d46b99668.tar.bz2 ghdl-e51f0ae6ee0a6c94b1a92b36dab7980d46b99668.zip |
synth: add testcase for issue 34
Diffstat (limited to 'testsuite/synth/issue34/tb_repro_rng1.vhdl')
-rw-r--r-- | testsuite/synth/issue34/tb_repro_rng1.vhdl | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/testsuite/synth/issue34/tb_repro_rng1.vhdl b/testsuite/synth/issue34/tb_repro_rng1.vhdl new file mode 100644 index 000000000..09f385a58 --- /dev/null +++ b/testsuite/synth/issue34/tb_repro_rng1.vhdl @@ -0,0 +1,34 @@ +entity tb_repro_rng1 is +end tb_repro_rng1; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_repro_rng1 is + signal clk : std_logic; + signal a : natural range 0 to 7; + signal b : natural range 0 to 7; +begin + dut: entity work.repro_rng1 + port map ( + clk => clk, a => a, b => b); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + a <= 1; + pulse; + assert b = 1 severity failure; + + a <= 6; + pulse; + assert b = 6 severity failure; + wait; + end process; +end behav; |