testsuite/synth: rename issueXX to synthXX for ghdlsynth-beta issues.

1 files changed, 0 insertions, 34 deletions

diff --git a/testsuite/synth/issue34/tb_repro_slv.vhdl b/testsuite/synth/issue34/tb_repro_slv.vhdl
deleted file mode 100644
index 45f0621eb..000000000
--- a/testsuite/synth/issue34/tb_repro_slv.vhdl
+++ /dev/null
@@ -1,34 +0,0 @@
-entity tb_repro_slv is
-end tb_repro_slv;
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-architecture behav of tb_repro_slv is
-  signal clk : std_logic;
-  signal a : std_logic_vector(7 downto 0);
-  signal b : std_logic_vector(7 downto 0);
-begin
-  dut: entity work.repro_slv
-    port map (
-      clk => clk, a => a, b => b);
-
-  process
-    procedure pulse is
-    begin
-      clk <= '0';
-      wait for 1 ns;
-      clk <= '1';
-      wait for 1 ns;
-    end pulse;
-  begin
-    a <= x"ab";
-    pulse;
-    assert b = x"ab" severity failure;
-
-    a <= x"12";
-    pulse;
-    assert b = x"12" severity failure;
-    wait;
-  end process;
-end behav;