testsuite/synth: testcase for conditional signal assignment.

1 files changed, 17 insertions, 0 deletions

diff --git a/testsuite/synth/issue40/testcase.vhdl b/testsuite/synth/issue40/testcase.vhdl
new file mode 100644
index 000000000..8055fac85
--- /dev/null
+++ b/testsuite/synth/issue40/testcase.vhdl
@@ -0,0 +1,17 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity testcase is
+        port(
+                data_in  : in std_ulogic;
+                data_out : out std_ulogic
+        );
+end entity testcase;
+
+architecture behaviour of testcase is
+begin
+        comb : process(all)
+        begin
+                data_out <= '1' when data_in = '0' else '0';
+        end process;
+end architecture behaviour;