synth: add testcase from issue8

1 files changed, 19 insertions, 0 deletions

diff --git a/testsuite/synth/issue8/tb_vector8_test1.vhdl b/testsuite/synth/issue8/tb_vector8_test1.vhdl
new file mode 100644
index 000000000..0a37884d5
--- /dev/null
+++ b/testsuite/synth/issue8/tb_vector8_test1.vhdl
@@ -0,0 +1,19 @@
+entity tb_vector8_test1 is
+end tb_vector8_test1;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_vector8_test1 is
+  signal r : std_logic;
+begin
+  dut: entity work.vector8_test1
+    port map (r);
+
+  process
+  begin
+    wait for 1 ns;
+    assert r = '1' severity failure;
+    wait;
+  end process;
+end behav;