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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-19 06:51:12 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-19 18:48:23 +0200 |
| commit | 51fb29f988e3d4d2cf2192fcc0f0a64d07f9d91e (patch) | |
| tree | 11c26c36ad2c026892997e5b3c8cab441fc28a65 /testsuite/synth/issue8/test3.vhdl | |
| parent | c9b3a23bfc75c9b2b74ed88cca97fb5a4e264d7f (diff) | |
| download | ghdl-51fb29f988e3d4d2cf2192fcc0f0a64d07f9d91e.tar.gz ghdl-51fb29f988e3d4d2cf2192fcc0f0a64d07f9d91e.tar.bz2 ghdl-51fb29f988e3d4d2cf2192fcc0f0a64d07f9d91e.zip | |
synth: add testcase from issue8
Diffstat (limited to 'testsuite/synth/issue8/test3.vhdl')
| -rw-r--r-- | testsuite/synth/issue8/test3.vhdl | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/synth/issue8/test3.vhdl b/testsuite/synth/issue8/test3.vhdl new file mode 100644 index 000000000..3e17936ca --- /dev/null +++ b/testsuite/synth/issue8/test3.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test3 is + port (led: out std_logic_vector (7 downto 0); + rst : std_logic; + clk : std_logic); +end test3; + +architecture synth of test3 is + signal int : std_logic_vector(1 downto 0); +begin +-- led(7) <= '0'; +-- led(6) <= '1'; +-- led(5) <= '0'; +-- led(3 downto 0) <= x"9"; + process (clk) is + begin + if rising_edge (clk) then + if rst = '1' then + int(1) <= '0'; + else + int(1) <= not int(1); + end if; + end if; + end process; + led(5) <= int (1); +end synth; |