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authorTristan Gingold <tgingold@free.fr>2021-12-06 20:47:31 +0100
committerTristan Gingold <tgingold@free.fr>2021-12-06 20:47:54 +0100
commitf5cb7116f863b69bcc9b93a52e8b7b9d62273fd7 (patch)
treeeb70942c2bcf2f7d73c865724f4554cdf4e42ae4 /testsuite/synth/issue938/ent.vhdl
parent88425cb365578cacd46939d93f837b2ac7b0d5e8 (diff)
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testsuite/synth: add a test for #938
Diffstat (limited to 'testsuite/synth/issue938/ent.vhdl')
-rw-r--r--testsuite/synth/issue938/ent.vhdl20
1 files changed, 20 insertions, 0 deletions
diff --git a/testsuite/synth/issue938/ent.vhdl b/testsuite/synth/issue938/ent.vhdl
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index 000000000..6d38a9548
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+++ b/testsuite/synth/issue938/ent.vhdl
@@ -0,0 +1,20 @@
+entity ent is
+ port (
+ r : in bit;
+ s : in bit;
+ q : out bit
+ );
+end entity;
+
+architecture a of ent is
+begin
+ process(r, s)
+ begin
+ if r = '1' then
+ q <= '0';
+ elsif s = '1' then
+ q <= '1';
+ end if;
+ end process;
+end;
+