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author | Tristan Gingold <tgingold@free.fr> | 2021-12-06 20:47:31 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-12-06 20:47:54 +0100 |
commit | f5cb7116f863b69bcc9b93a52e8b7b9d62273fd7 (patch) | |
tree | eb70942c2bcf2f7d73c865724f4554cdf4e42ae4 /testsuite/synth/issue938/latches.vhdl | |
parent | 88425cb365578cacd46939d93f837b2ac7b0d5e8 (diff) | |
download | ghdl-f5cb7116f863b69bcc9b93a52e8b7b9d62273fd7.tar.gz ghdl-f5cb7116f863b69bcc9b93a52e8b7b9d62273fd7.tar.bz2 ghdl-f5cb7116f863b69bcc9b93a52e8b7b9d62273fd7.zip |
testsuite/synth: add a test for #938
Diffstat (limited to 'testsuite/synth/issue938/latches.vhdl')
-rw-r--r-- | testsuite/synth/issue938/latches.vhdl | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/issue938/latches.vhdl b/testsuite/synth/issue938/latches.vhdl new file mode 100644 index 000000000..0fcd7a8ba --- /dev/null +++ b/testsuite/synth/issue938/latches.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity latches is + port( + G, D, CLR : in std_logic; + Q : out std_logic + ); +end latches; + +architecture archi of latches is +begin + process(CLR, D, G) + begin + if (CLR = '1') then + Q <= '0'; + elsif (G = '1') then + Q <= D; + end if; + end process; +end archi; |