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authorTristan Gingold <tgingold@free.fr>2021-12-06 20:47:31 +0100
committerTristan Gingold <tgingold@free.fr>2021-12-06 20:47:54 +0100
commitf5cb7116f863b69bcc9b93a52e8b7b9d62273fd7 (patch)
treeeb70942c2bcf2f7d73c865724f4554cdf4e42ae4 /testsuite/synth/issue938/tb_latches.vhdl
parent88425cb365578cacd46939d93f837b2ac7b0d5e8 (diff)
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testsuite/synth: add a test for #938
Diffstat (limited to 'testsuite/synth/issue938/tb_latches.vhdl')
-rw-r--r--testsuite/synth/issue938/tb_latches.vhdl52
1 files changed, 52 insertions, 0 deletions
diff --git a/testsuite/synth/issue938/tb_latches.vhdl b/testsuite/synth/issue938/tb_latches.vhdl
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+entity tb_latches is
+end tb_latches;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_latches is
+ signal g : std_logic;
+ signal d : std_logic;
+ signal clr : std_logic;
+ signal q : std_logic;
+begin
+ dut: entity work.latches
+ port map (g, d, clr, q);
+
+ process
+ begin
+ clr <= '1';
+ g <= '0';
+ wait for 1 ns;
+ assert q = '0' severity failure;
+
+ clr <= '0';
+ wait for 1 ns;
+ assert q = '0' severity failure;
+
+ g <= '1';
+ d <= '1';
+ wait for 1 ns;
+ assert q = '1' severity failure;
+
+ g <= '0';
+ d <= '0';
+ wait for 1 ns;
+ assert q = '1' severity failure;
+
+ g <= '1';
+ d <= '0';
+ wait for 1 ns;
+ assert q = '0' severity failure;
+
+ g <= '1';
+ d <= '1';
+ wait for 1 ns;
+ assert q = '1' severity failure;
+
+ clr <= '1';
+ wait for 1 ns;
+ assert q = '0' severity failure;
+ wait;
+ end process;
+end behav;