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author | Tristan Gingold <tgingold@free.fr> | 2019-10-08 20:24:42 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-08 20:24:42 +0200 |
commit | 7678d2865436245e081a0a070a784d321442f513 (patch) | |
tree | c9e5f3bdc986dfb17ee68193139497caca06ff58 /testsuite/synth/issue973/tb_ent.vhdl | |
parent | 9fc6a1b3e2b83dbed76f6792e72034f1bcb056ef (diff) | |
download | ghdl-7678d2865436245e081a0a070a784d321442f513.tar.gz ghdl-7678d2865436245e081a0a070a784d321442f513.tar.bz2 ghdl-7678d2865436245e081a0a070a784d321442f513.zip |
testsuite/syn: add testcase for #973
Diffstat (limited to 'testsuite/synth/issue973/tb_ent.vhdl')
-rw-r--r-- | testsuite/synth/issue973/tb_ent.vhdl | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/testsuite/synth/issue973/tb_ent.vhdl b/testsuite/synth/issue973/tb_ent.vhdl new file mode 100644 index 000000000..328d48180 --- /dev/null +++ b/testsuite/synth/issue973/tb_ent.vhdl @@ -0,0 +1,22 @@ +entity tb_ent is +end tb_ent; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_ent is + signal i : std_logic_vector (7 downto 0); + signal o : std_logic_vector (3 downto 0); +begin + dut: entity work.ent + port map (i, o); + + process + begin + i <= x"b6"; + wait for 1 ns; + assert o = x"b" severity failure; + + wait; + end process; +end behav; |