synth: add tests for partial assignment.

1 files changed, 27 insertions, 0 deletions

diff --git a/testsuite/synth/output01/tb_output01.vhdl b/testsuite/synth/output01/tb_output01.vhdl
new file mode 100644
index 000000000..1eacded14
--- /dev/null
+++ b/testsuite/synth/output01/tb_output01.vhdl
@@ -0,0 +1,27 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_output01 is
+end tb_output01;
+
+architecture behav of tb_output01 is
+  signal i : std_logic;
+  signal o : std_logic_vector (1 downto 0);
+begin
+  inst: entity work.output01
+    port map (i => i, o => o);
+
+  process
+  begin
+    i <= '0';
+    wait for 1 ns;
+    assert o = "10" severity failure;
+
+    i <= '1';
+    wait for 1 ns;
+    assert o = "01" severity failure;
+
+    wait;
+  end process;
+end behav;
+