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author | Tristan Gingold <tgingold@free.fr> | 2019-10-07 18:26:32 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-07 18:26:32 +0200 |
commit | 8d3778ffbb30ecb023bd1989d938f6cf83e1436c (patch) | |
tree | a4a9cd5c3bb458d8c58faa0afb7da7f4145d975d /testsuite/synth/pkg01/mixer.vhdl | |
parent | 27ce4a93d4bfc66dc50eadcf59375b4ac541c66a (diff) | |
download | ghdl-8d3778ffbb30ecb023bd1989d938f6cf83e1436c.tar.gz ghdl-8d3778ffbb30ecb023bd1989d938f6cf83e1436c.tar.bz2 ghdl-8d3778ffbb30ecb023bd1989d938f6cf83e1436c.zip |
testsuite/synth: add pkg01
Diffstat (limited to 'testsuite/synth/pkg01/mixer.vhdl')
-rw-r--r-- | testsuite/synth/pkg01/mixer.vhdl | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/testsuite/synth/pkg01/mixer.vhdl b/testsuite/synth/pkg01/mixer.vhdl new file mode 100644 index 000000000..92ed2c78e --- /dev/null +++ b/testsuite/synth/pkg01/mixer.vhdl @@ -0,0 +1,15 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity mixer is + port (h, l : std_logic_vector(7 downto 0); + o : out std_logic_vector (7 downto 0)); +end mixer; + +architecture behav of mixer is + signal t1 : std_logic_vector (7 downto 0); +begin + a1: entity work.cmask + port map (l, t1); + o <= t1 or h; +end behav; |