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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-20 04:46:26 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-20 04:46:26 +0200 |
| commit | b77eb1a27fa6838c7194a44f8d872005d08e6ac7 (patch) | |
| tree | 82433c97f5271cae91191301b72e5bfbf63b8067 /testsuite/synth/psl02/verif1.vhdl | |
| parent | d81dfb85709da4daa9bac3fceec5716a0b410b5b (diff) | |
| download | ghdl-b77eb1a27fa6838c7194a44f8d872005d08e6ac7.tar.gz ghdl-b77eb1a27fa6838c7194a44f8d872005d08e6ac7.tar.bz2 ghdl-b77eb1a27fa6838c7194a44f8d872005d08e6ac7.zip | |
testsuite/synth: add psl02
Diffstat (limited to 'testsuite/synth/psl02/verif1.vhdl')
| -rw-r--r-- | testsuite/synth/psl02/verif1.vhdl | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/testsuite/synth/psl02/verif1.vhdl b/testsuite/synth/psl02/verif1.vhdl new file mode 100644 index 000000000..5aeb9559f --- /dev/null +++ b/testsuite/synth/psl02/verif1.vhdl @@ -0,0 +1,5 @@ +vunit verif1 (assert2) +{ + default clock is rising_edge(clk); + assert always cnt /= 5 abort rst; +} |