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author | Tristan Gingold <tgingold@free.fr> | 2020-03-11 21:22:39 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-13 06:30:30 +0100 |
commit | 6c42b0a550549f7cc0f189fce3c72f069a4d336d (patch) | |
tree | 56463ef1ca71ede9ced41502038317dbc059a214 /testsuite/synth/range01/revrng01.vhdl | |
parent | 8bb20d4d61d72528ff858962b505e11ca19179da (diff) | |
download | ghdl-6c42b0a550549f7cc0f189fce3c72f069a4d336d.tar.gz ghdl-6c42b0a550549f7cc0f189fce3c72f069a4d336d.tar.bz2 ghdl-6c42b0a550549f7cc0f189fce3c72f069a4d336d.zip |
testsuite/synth: add a test for previous commit.
Diffstat (limited to 'testsuite/synth/range01/revrng01.vhdl')
-rw-r--r-- | testsuite/synth/range01/revrng01.vhdl | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/range01/revrng01.vhdl b/testsuite/synth/range01/revrng01.vhdl new file mode 100644 index 000000000..865d1dab8 --- /dev/null +++ b/testsuite/synth/range01/revrng01.vhdl @@ -0,0 +1,21 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity revrng01 is + port (a : std_logic_vector (7 downto 0); + o : out std_logic_vector (7 downto 0)); +end revrng01; + +architecture behav of revrng01 is + function rev (v : std_logic_vector) return std_logic_vector + is + variable temp : std_logic_vector(v'reverse_range); + begin + for i in v'range loop + temp (i) := v (i); + end loop; + return temp; + end rev; +begin + o <= rev (a); +end behav; |