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author | Tristan Gingold <tgingold@free.fr> | 2019-09-05 11:15:33 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-05 11:15:33 +0200 |
commit | 6a933a7d9b2738e388018db056e4dfbd52ec8021 (patch) | |
tree | 8d0e0799adccfa70898f52e2b2220a50ef621ba2 /testsuite/synth/rec01/tb_rec01.vhdl | |
parent | 7585dba6b20036cd981d0434d27643f4a5a80244 (diff) | |
download | ghdl-6a933a7d9b2738e388018db056e4dfbd52ec8021.tar.gz ghdl-6a933a7d9b2738e388018db056e4dfbd52ec8021.tar.bz2 ghdl-6a933a7d9b2738e388018db056e4dfbd52ec8021.zip |
testsuite/synth: add test for previous commit.
Diffstat (limited to 'testsuite/synth/rec01/tb_rec01.vhdl')
-rw-r--r-- | testsuite/synth/rec01/tb_rec01.vhdl | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/testsuite/synth/rec01/tb_rec01.vhdl b/testsuite/synth/rec01/tb_rec01.vhdl new file mode 100644 index 000000000..da9e0ff38 --- /dev/null +++ b/testsuite/synth/rec01/tb_rec01.vhdl @@ -0,0 +1,42 @@ +entity tb_rec01 is +end tb_rec01; + +library ieee; +use ieee.std_logic_1164.all; +use work.rec01_pkg.all; + +architecture behav of tb_rec01 is + signal inp : myrec; + signal clk : std_logic; + signal rst : std_logic; + signal r : std_logic; +begin + dut: entity work.rec01 + port map (inp => inp, clk => clk, rst => rst, o => r); + + process + procedure pulse is + begin + clk <= '0'; + wait for 1 ns; + clk <= '1'; + wait for 1 ns; + end pulse; + begin + rst <= '1'; + pulse; + assert r = '1' severity failure; + + rst <= '0'; + inp <= (a => "0010", b => '1'); + pulse; + assert r = '1' severity failure; + + rst <= '0'; + inp <= (a => "0001", b => '1'); + pulse; + assert r = '0' severity failure; + + wait; + end process; +end behav; |